The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventor hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Multi-level cell (MLC) NAND Flash memory is becoming popular as its cost per unit of data storage decreases relative to the cost of single-level cell (SLC) NAND Flash memory. However, because more than one bit of information is stored in each cell, MLC NAND Flash memory also experiences a higher raw bit error rate than SLC NAND Flash memory.
In order to meet reliability requirements, more advanced error correction schemes may be used in MLC NAND Flash memory devices than in SLC NAND Flash memory devices. However, the complexity of advanced error correction schemes, such as read-retry decoding and soft-decision decoding, can increase the latency of NAND Flash memory data access operations. The effect of data access latency will differ for different applications. For example, some critical operations, such as host data read, may require relatively low memory access latency, while other operations such as some background operations—e.g., data accesses for garbage collection—may be less sensitive to the degree of latency.